# $Id$

PortSystem       1.0

name             veriwell
version          2.8.6
categories       science
maintainers      nomaintainer
description      VeriWell Verilog Simulator

long_description \
     VeriWell is a full Verilog simulator. It supports nearly all of the \
     IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the \
     same simulator that was sold by Wellspring Solutions in the mid-1990 \
     and was included with the Thomas and Moorby book

homepage         http://sourceforge.net/projects/veriwell
platforms        darwin
master_sites     sourceforge
checksums        md5 adffd9b8e2b461d75ab01db2bdb1563b \
                 sha1 f98b11ca09fe1fc38b9c9be33d2bf127e0fee42d \
                 rmd160 9ca3ad3b71a8de4f50108738317be244aa350461

depends_build    port:help2man
depends_lib      port:bzip2 \
                 port:readline \
                 port:zlib

use_parallel_build   yes

#  The following prevent conflicts with other Verilog simulators
#  that may have installed their own copies of:
#  acc_user.h  veriuser.c  veriuser.h

configure.args  --includedir=${prefix}/include/veriwell

post-destroot {
    set docdir ${destroot}${prefix}/share/doc/${name}-${version}
    xinstall -d ${docdir}
    xinstall -W ${worksrcpath} \
        ChangeLog \
        README \
        TODO \
        ${docdir}
}

livecheck.regex "<title>VeriWell ${name} (.*) released.*</title>"