# $Id$

PortSystem       1.0

name             veriwell
version          2.8.7
categories       science
license          GPL-2+
maintainers      nomaintainer
description      VeriWell Verilog Simulator

long_description \
     VeriWell is a full Verilog simulator. It supports nearly all of the \
     IEEE1364-1995 standard, as well as PLI 1.0. VeriWell is the \
     same simulator that was sold by Wellspring Solutions in the mid-1990 \
     and was included with the Thomas and Moorby book

homepage         http://sourceforge.net/projects/veriwell
platforms        darwin
master_sites     sourceforge
checksums           md5     bf686d4f96d3ff8fb08616da157888fb \
                    sha1    9ef4e6a25a4fd65db325a89ed89b199547fabbd6 \
                    rmd160  3d86c40b353f701d61cab301e0f7c3ec136c88e7

depends_build    port:help2man
depends_lib      port:bzip2 \
                 port:readline \
                 port:zlib

use_parallel_build   yes

#  The following prevent conflicts with other Verilog simulators
#  that may have installed their own copies of:
#  acc_user.h  veriuser.c  veriuser.h

configure.args  --includedir=${prefix}/include/veriwell

post-destroot {
    set docdir ${destroot}${prefix}/share/doc/${name}
    xinstall -d ${docdir}
    xinstall -m 644 -W ${worksrcpath} \
        ChangeLog AUTHORS COPYING NEWS README TODO \
        lxt/LXT_Explained.html \
        ${docdir}
}

livecheck.regex "<title>VeriWell ${name} (.*) released.*</title>"